1. Field of the Invention
This invention relates generally to high-speed, high-drive output buffer circuits and more particularly, it relates to CMOS output buffer circuits which includes negative feedback means for significantly reducing voltage oscillation.
2. Description of the Prior Art
As is well-know in the art, digital logic circuits are widely used in the areas of electronics and computer-type equipment. Specifically, one such use of digital logic circuits is to provide an interface function between one logic type of a first integrated circuit device and another logic type of a second integrated circuit device. An output buffer circuit is an important component for this interface function. The output buffer circuit provides, when enabled, an output signal which is a function of a data input signal received from other logic circuitry of the integrated circuit.
In FIG. 1, there is shown a simplified schematic circuit diagram of a portion of a typical output buffer 10 which is formed as a part of a semiconductor integrated circuit chip 12. The output buffer circuit 10 includes a pull-up transistor device 14 and a pull-down transistor device 16 connected in series between respective first and second power supply pads 18, 20. The first power supply pad 18 may be supplied with a positive potential or voltage VCC (typically at +5.0 volts) which is connected to an internal power supply potential node VL2 via a lead line having parasitic inductance L2. The source of the P-channel field-effect transistor 14 is also connected to the node VL2. The parasitic inductance L2 represents a package inductance associated with the pad 18 itself and the bond wire used to connect the source of the transistor 14 to the pad 18. The second power supply pad 20 may be supplied with a ground potential VSS (typically at 0 volts) which is connected to an internal ground potential node VL1 via lead line having parasitic inductance L1. A source of the N-channel field-effect transistor 16 is also connected to the node VL1. The parasitic inductance L1 represents a package inductance associated with the pad 20 itself and the bond wire used to connect the source of the transistor 16 to the pad 20.
The drains of the transistors 14 and 16 are connected together and are further joined to an internal node 22. The internal node 22 is also connected to an output pad 24 via a lead connection having parasitic inductance L3. The parasitic inductance L3 represents a package inductance associated with the output pad 24 itself and the bond wire used to connect the drains of the transistors 14, 16 to the pad 24. The output of the pad 24 of the buffer circuit 10 is used to drive a capacitive load represented by capacitor CAP and connected between the pad 24 and the ground potential VSS. The capacitor CAP defines the load that the output pad sees and is the sum of the individual capacitances of all the devices being driven as well as the board capacitance.
The control circuitry 26 has a first input on line 28 for receiving a data input signal DATAIN and a second input on line 30 for receiving an enable signal ENABLE. The control circuitry 26 has a first control signal ENUP on line 32 connected to the gate of the P-channel pull-up transistor 14 and a second control signal ENDN on line 34 connected to the gate of the N-channel pull-down transistor 16.
Dependent upon the logic state of the data input signal and the enable signal, either the pull-up transistor 14 or the pull-down transistor 16 is quickly turned off and the other one of them is turned on. Such rapid switching off and on of the pull-up and pull-down transistor devices causes sudden surges of current creating what is commonly known as current spikes. As a result, when the internal node 22 is making a high-to-low transition, oscillation or inductive ringing appears at the output pad 24 referred to as "ground bounce." This "ground bounce" is defined to be undershooting of the ground potential followed by a dampening oscillation around it. This is a major problem in high-speed output buffer circuits. The higher the value of the inductance and the lower the value of the capacitance, the more severe will be the "ground bounce."
Similarly, when the internal output node 22 is making a low-to-high transition, oscillation or inductive ringing will appear at the output pad 24 which will overshoot the positive supply potential. This overshoot is sometimes referred to as "supply bounce."
Also, during such output switching, charging and discharging currents from the pull-up and pull-down transistor devices will flow through the package inductances of the power supply and ground lines so as to cause inductive noise at the internal power supply potential node VL2 and at the internal ground potential node VL1. These internal supply and ground noises are undesirable since they will degrade the output voltage levels (logic "1" and logic "0") causing interface problems among the output buffer circuit and other integrated circuits.
Various approaches have been made in the prior art of output buffer design to minimize the undesired ground bounce and the supply and ground noises without sacrificing the needed high-speed of operation. One technique is described and illustrated in U.S. Pat. No. 4,877,980 issued on Oct. 31, 1989, and entitled "Time Variant Drive Circuit For High Speed Bus Driver To Limit Oscillation Or Ringing On A Bus." This '980 patent discloses a drive circuit which modifies a digital drive signal to produce a time variant drive signal for application to a gate of a bus driver transistor in order to reduce the amplitude of ringing on a bus. The drive circuit includes a P-channel MOS transistor and an N-channel MOS transistor which are connected so that the digital drive signal is simultaneously applied to the source of the P-channel transistor and to the drain of the N-channel transistor. The gate of the bus driver transistor is connected to the drain of the P-channel transistor and to the source of the N-channel transistor. A bias voltage is applied to one of the gates of the P-channel and N-channel transistors so that application of the digital drive signal to the drive circuit will cause the N-channel transistor to rapidly apply a limited drive signal to the gate of the driver transistor and will cause the P-channel transistor to apply a gradually increasing drive signal to the gate of the driver transistor, thereby preventing objectionable ringing on the bus.
A second technique is described and shown in U.S. Pat. No. 5,321,319 issued on Jun. 14, 1994, and entitled "High Speed CMOS Bus Driver Circuit That Provides Minimum Output Signal Oscillation." This '319 patent discloses a high speed bus driver circuit which includes first and second drive transistors and first and second reference voltage generators coupled to the respective first and second drive transistors. The reference voltage generators serve to provide clamping voltages at certain threshold levels at the gates of the first and second drive transistors and to provide propagation delay for driving up and down signals, respectively. In FIGS. 3(a) and 3(b), the reference generators are formed by voltage divider comprised of a load transistor and a plurality of saturated series driver transistors. In the alternate embodiment of FIGS. 4(a) and 4(b), the reference generators have been modified slightly from the ones in FIGS. 3(a) and 3(b) so as to convert the same into a current mirror configuration. As a result, there is provided a controlled slew rate and a clamp voltage on the gates of the bus drive transistor so as to minimize the voltage oscillation on the bus.
Further, a third technique is depicted in U.S. Pat. No. 5,248,906 issued on Sep. 28, 1993, and entitled "High Speed CMOS Output Buffer Circuit Minimizes Output Signal Oscillation and Steady State Current." This '906 patent teaches a high speed output buffer for minimizing output signal oscillation and steady state current which includes first and second driver transistors, a pair of reference voltage generators, means for providing a controlled ramping of the output voltage, and means for shutting down the pair of reference generators after the output oscillation has subsided to some acceptable level. In FIGS. 3(a) and 3(b), the reference generators illustrated are similar to those shown in FIGS. 4(b) and 4(a) of the '319 patent.
It will be noted that the above-described '980, '319, and '906 patents are all assigned to the same assignee as the present invention and are hereby incorporated by reference. The present invention represents a significant improvement over these aforementioned patents so as to further minimize the voltage oscillation on the bus. This is achieved by the provision of negative feedback means coupled between the internal power supply potential/ground potential node and the gate of the pull-up/pull-down drive transistor.